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d a t a sh eet preliminary speci?cation supersedes data of 1995 sep 21 file under integrated circuits, ic22 1996 jul 08 integrated circuits saa7188a digital video encoder (denc2-m)
1996 jul 08 2 philips semiconductors preliminary speci?cation digital video encoder (denc2-m) saa7188a features cmos 5 v device digital pal/ntsc encoder system pixel frequency 13.5 mhz accepts mpeg decoded data 8-bit wide mpeg port input data format cb, y, cr, etc. (ccir 656) 16-bit wide yuv input port i 2 c-bus control port or alternatively mpu parallel control port encoder can be master or slave programmable horizontal and vertical input synchronization phase programmable horizontal sync output phase osd overlay with look-up tables (luts) 8 3 bytes colour bar generator line 21 closed caption encoder macrovision pay-per-view copy protection system as option the device is protected by usa patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. use of the macrovision anti-copy process in the device is licensed for non-commercial home use only, which is its sole intended use in this device. please contact your nearest philips semiconductors sales office for more information. cross-colour reduction dacs operating at 27 mhz with 10-bit resolution controlled rise/fall times of output syncs and blanking down-mode of dacs cvbs and s-video output simultaneously plcc68 package. general description the saa7188a encodes digital yuv video data to an ntsc, pal cvbs or s-video signal. the circuit accepts ccir compatible yuv data with 720 active pixels per line in 4:2:2 multiplexed formats, e.g. mpeg decoded data. it includes a sync/clock generator and on-chip digital-to-analog converters (dacs). the circuit is compatible to the dig-tv2 chip family. quick reference data symbol parameter min. typ. max. unit v dda analog supply voltage 4.75 5.0 5.25 v v ddd digital supply voltage 4.5 5.0 5.5 v i dda analog supply current - 50 55 ma i ddd digital supply current - 140 170 ma v i input signal voltage levels ttl compatible v o(p-p) analog output signal voltages y, c and cvbs without load (peak-to-peak value) - 2 - v r l load resistance 80 --w ile lf integral linearity error -- 2 lsb dle lf differential linearity error -- 1 lsb t amb operating ambient temperature 0 - +70 c
1996 jul 08 3 philips semiconductors preliminary speci?cation digital video encoder (denc2-m) saa7188a ordering information block diagram type number package name description version SAA7188AWP plcc68 plastic leaded chip carrier; 68 leads sot188-2 o k, full pagewidth control interface data manager encoder internal control bus clock timing signals output interface sync clk a v ddd1 to v ddd3 48,50, 54,56 d 55 47 53 51 49 52 46 43 rtci v refh v dda4 v dda1 88 saa7188a 8 8 8 8 8 mp7 to mp0 vp0 to vp7 8 61 68 sel_mpu cs/sa 1,8,19 28,35, 42,62 dp0 to dp7 v ssd1 v ssd7 63 to 66 2 to 5 59 60 58 57 41 40 38 39 36 6 7 31 key sel_ed osd0 to osd2 32 to 34 20 to 27 9 to 16 18 29 rcm1 rcm2 30 17,37,67 to rw/scl a0/sda dtack reset xtali xtalo llc cref cdir rcv1 rcv2 cvbs y to i i chroma v ssa v refl mbg266 fig.1 block diagram.
1996 jul 08 4 philips semiconductors preliminary speci?cation digital video encoder (denc2-m) saa7188a pinning symbol pin description v ssd1 1 digital ground 1 dp4 2 upper 4 bits of the data port. if pin 68 (sel_mpu) is high, this is the data bus of the parallel mpu interface. if it is low, they are the uv lines of the video port. dp5 3 dp6 4 dp7 5 rcv1 6 raster control 1 for video port. depending on the synchronization mode, this pin receives/provides a vs/fs/fseq signal. rcv2 7 raster control 2 for video port. depending on the synchronization mode, this pin receives/provides an hs/href/cbl signal. v ssd2 8 digital ground 2 vp0 9 video port. this is an input for ccir 656 compatible, multiplexed video data. if the 16-bit dig-tv2 format is used, this is the y data. vp1 10 vp2 11 vp3 12 vp4 13 vp5 14 vp6 15 vp7 16 v ddd1 17 digital supply voltage 1 sel_ed 18 select encoder data. selects data either from mpeg port or from video port as encoder input. v ssd3 19 digital ground 3 mp7 20 mpeg port. it is an input for ccir 656 style multiplexed yuv data. mp6 21 mp5 22 mp4 23 mp3 24 mp2 25 mp1 26 mp0 27 v ssd4 28 digital ground 4 rcm1 29 raster control 1 for mpeg port. this pin provides a vs/fs/fseq signal. rcm2 30 raster control 2 for mpeg port. this pin provides an hs pulse for the mpeg decoder. key 31 key signal for osd. it is active high. osd0 32 on-screen display data. this is the index for the internal osd look-up table. osd1 33 osd2 34 v ssd5 35 digital ground 5 cdir 36 clock direction. if the cdir input is high, the circuit receives a clock signal, otherwise llc and cref are generated by the internal crystal oscillator. v ddd2 37 digital supply voltage 2
1996 jul 08 5 philips semiconductors preliminary speci?cation digital video encoder (denc2-m) saa7188a llc 38 line-locked clock. this is the 27 mhz master clock for the encoder. the direction is set by the cdir pin. cref 39 clock reference signal. this is the clock quali?er for dig-tv2 compatible signals. xtalo 40 crystal oscillator output (to crystal). xtali 41 crystal oscillator input (from crystal). if the oscillator is not used, this pin should be connected to ground. v ssd6 42 digital ground 6 rtci 43 real time control input. if the clock is provided by an saa7151b, rtci should be connected to the rtco pin of the decoder to improve the signal quality. ap 44 test pin. connect to digital ground for normal operation. sp 45 test pin. connect to digital ground for normal operation. v refl 46 lower reference voltage input for the dacs. v refh 47 upper reference voltage input for the dacs. v dda1 48 analog positive supply voltage 1 for the dacs and output ampli?ers. chroma 49 analog output of the chrominance signal. v dda2 50 analog supply voltage 2 for the dacs and output ampli?ers. y 51 analog output of the luminance signal. v ssa 52 analog ground for the dacs and output ampli?ers. cvbs 53 analog output of the cvbs signal. v dda3 54 analog supply voltage 3 for the dacs and output ampli?ers. i i 55 current input for the output ampli?ers, connect via a 15 k w resistor to v dda . v dda4 56 analog supply voltage 4 for the dacs and output ampli?ers. reset 57 reset input, active low. after reset is applied, all outputs are in 3-state input mode. the i 2 c-bus receiver waits for the start condition. dt ack 58 data acknowledge output of the parallel mpu interface, active low, otherwise high impedance. r w/scl 59 if pin 68 (sel_mpu) is high, this is the read/write signal of the parallel mpu interface, otherwise it is the i 2 c-bus serial clock input. a0/sda 60 if pin 68 (sel_mpu) is high, this is the address signal of the parallel mpu interface, otherwise it is the i 2 c-bus serial data input/output. cs/sa 61 if pin 68 (sel_mpu) is high, this is the chip select signal of the parallel mpu interface, otherwise it is the i 2 c-bus slave address select pin. low: slave address = 88h, high = 8ch. v ssd7 62 digital ground 7 dp0 63 lower 4 bits of the data port. if pin 68 (sel_mpu) is high, this is the data bus of the parallel mpu interface. if it is low, they are the uv lines of the video port. dp1 64 dp2 65 dp3 66 v ddd3 67 digital supply voltage 3 sel_mpu 68 select mpu interface input. if it is high, the parallel mpu interface is active, otherwise the i 2 c-bus interface will be used. symbol pin description
1996 jul 08 6 philips semiconductors preliminary speci?cation digital video encoder (denc2-m) saa7188a fig.2 pin configuration. handbook, full pagewidth mbg265 saa7188a 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 61 62 63 64 65 66 67 68 1 2 3 4 5 6 7 8 9 vp1 vp2 vp3 vp4 vp5 vp6 vp7 mp7 mp6 mp5 mp4 mp3 mp2 mp1 sel_ed v ddd1 v ssd3 ap sp chroma y cvbs reset v refl v refh v dda1 v dda2 v dda3 v dda4 i i v ssa mp0 key osd0 osd1 osd2 cdir cref xtalo xtali rtci llc rcm1 rcm2 v ssd4 v ssd5 v ddd2 v ssd6 cs/sa dp0 dp1 dp2 dp3 dp4 dp5 dp6 dp7 vp0 rcv1 rcv2 sel_mpu v ssd7 v ddd3 v ssd1 v ssd2 dtack rw/scl a0/sda
1996 jul 08 7 philips semiconductors preliminary speci?cation digital video encoder (denc2-m) saa7188a functional description the digital mpeg-compatible video encoder (denc2-m) encodes digital luminance and chrominance into analog cvbs and simultaneously s-video (y/c) signals. ntsc-m and pal b/g standards also sub-standards are supported. the basic encoder function consists of subcarrier generation and colour modulation also insertion of synchronization signals. luminance and chrominance signals are filtered in accordance with the standard requirements rs-170-a and ccir 624. for ease of analog post filtering the signals are twice oversampled with respect to pixel clock before digital-to-analog conversion. for total filter transfer characteristics see figs 3 to 6. the dacs are realized with full 10-bit resolution. the encoder provides three 8-bit wide data ports, that serve different applications. the mpeg port (mp) and the video port (vp) accept 8 lines multiplexed cb-y-cr data. the video port (vp) is also able to handle dig-tv2 family compatible 16-bit yuv signals. in this event, the data port (dp) is used for the u/v components. the data port can alternatively handle the data of an 8-bit wide microprocessor interface. the 8-bit multiplexed cb-y-cr formats are ccir 656 (d1 format) compatible, but the sav, eav etc. codes are not decoded. a crystal-stable master clock (llc) of 27 mhz, which is twice the ccir line-locked pixel clock of 13.5 mhz, needs to be supplied externally. optionally, a crystal oscillator input/output pair of pins and an on-chip clock driver is provided. additionally, a dmsd2 compatible clock interface, using cref (input or output) and rtc (see data sheet saa7151b ) is available. the denc2-m synthesizes all necessary internal signals, colour subcarrier frequency, and synchronization signals, from that clock. denc2-m is always timing master for the mpeg port (mp), but it can additionally be configured as master or slave for the video port (vp). the ic also contains closed caption and extended data services encoding (line 21) and supports anti-taping signal generation in accordance with macrovision; it also supports osd via key and three-bit overlay techniques by a 24 8 lut. the ic can be programmed via i 2 c-bus or 8-bit mpu interface, but only one interface configuration can be active at a time; if the 16-bit video port mode (vp and dp) is being used, only the i 2 c-bus interface can be selected. a number of possibilities are provided for setting of different video parameters such as: black and blanking level control colour subcarrier frequency variable burst amplitude etc. during reset ( reset = low) and after reset is released, all digital i/o stages are set to input mode. a reset forces the control interfaces to abort any running bus transfer and to set register 3ah to contents 13h, register 61h to contents 15h, and register 6ch to contents 00h. all other control registers are not influenced by a reset. data manager in the data manager, real time arbitration on the data stream to be encoded is performed. depending on hardware conditions (signals on pins sel_ed, key, osd2 to osd0, mp7 to to mp0, vp7 to vp0 and dp7 to dp0) and different software programming either data from the mp port, from the vp port, or from the osd port are selected to be encoded to cvbs and y/c signals. optionally, the osd colour look-up tables located in this block, can be read out in a pre-defined sequence (8 steps per active video line), achieving e.g. a colour bar test pattern generator without need for an external data source. the colour bar function is only under software control.
1996 jul 08 8 philips semiconductors preliminary speci?cation digital video encoder (denc2-m) saa7188a encoder v ideo path the encoder generates out of y, u and v baseband signals luminance and colour subcarrier output signals, suitable for use as cvbs or separate y/c signals. luminance is modified in gain and in offset (latter programmable in a certain range to enable different black level set-ups). after having been inserted a fixed synchronization level, in accordance with standard composite synchronization schemes, a variable blanking level, programmable also in a certain range to allow for manipulations with macrovision anti-taping, additional insertion of agc super white pulses, programmable in height, is supported. in order to enable easy analog post filtering, luminance is interpolated from 13.5 mhz data rate to 27 mhz data rate, providing luminance in 10-bit resolution. this filter is also used to define smoothed transients for synchronization pulses and blanking period. for transfer characteristic of the luminance interpolation filter see figs 5 and 6. chrominance is modified in gain (programmable separately for u and v), standard dependent burst is inserted, before baseband colour signals are interpolated from 6.75 mhz data rate to 27 mhz data rate. one of the interpolation stages can be bypassed, thus providing a higher colour bandwidth, which can be made use of for y/c output. for transfer characteristics of the chrominance interpolation filter see figs 3 and 4. the amplitude of inserted burst is programmable in a certain range, suitable for standard signals and for special effects. behind the succeeding quadrature modulator, colour in 10-bit resolution is provided on subcarrier. the numeric ratio between y and c outputs is in accordance with set standards. c losed c aption e ncoder using this circuit, data in accordance with the specification of closed caption or extended data service, delivered by the control interface, can be encoded (line 21). two dedicated pairs of bytes (two bytes per field), each pair preceded by run-in clocks and framing code, are possible. the actual line number where data is to be encoded in, can be modified in a certain range. data clock frequency is in accordance with definition for ntsc-m standard 32 times horizontal line frequency. data low at the output of the dacs corresponds to 0 ire, data high at the output of the dacs corresponds to approximately 50 ire. it is also possible to encode closed caption data for 50 hz field frequencies at 32 times horizontal line frequency. output interface in the output interface encoded y and c signals are converted from digital-to-analog in 10-bit resolution both y and c signals are combined to a 10-bit cvbs signal, also; in front of the summation point, the luminance signal can optionally be fed through a further filter stage, suppressing components in the range of subcarrier frequency. thus, a type of cross colour reduction is provided, which is useful in a standard tv set with cvbs input. slopes of synchronization pulses are not affected with any cross colour reduction active. three different filter characteristics or bypass are available, see fig.5. the cvbs output occurs with the same processing delay as the y and c outputs. absolute amplitudes at the input of the dac for cvbs is reduced by 15 16 with respect to y and c dacs to make maximum use of conversion ranges. outputs of all dacs can be set together via software control to minimum output voltage for either purpose. synchronization the synchronization of the denc2-m is able to operate in two modes; slave mode and master mode. in the slave mode, the circuit accepts synchronization pulses at the bidirectional rcv1 port. the timing and trigger behaviour related to the video signal on vp (and dp, if used) can be influenced by programming the polarity and on-chip delay of rcv1. active slope of rcv1 defines the vertical phase and optionally the odd/even and colour frame phase to be initialized, it can be also used to set the horizontal phase. if the horizontal phase is not be influenced by rcv1, a horizontal pulse needs to be supplied at the rcv2 pin. timing and trigger behaviour can also be influenced for rcv2. if there are missing pulses at rcv1 and/or rcv2, the time base of denc2-m runs free, thus an arbitrary number of synchronization slopes may miss, but no additional pulses (such with wrong phase) must occur.
1996 jul 08 9 philips semiconductors preliminary speci?cation digital video encoder (denc2-m) saa7188a if the vertical and horizontal phase is derived from rcv1, rcv2 can be used for horizontal or composite blanking input or output. in the master mode, the time base of the circuit continuously runs free. on the rcv1 port, the ic can output: a vertical sync signal (vs) with 3 or 2.5 lines duration, or an odd/even signal which is low in odd fields, or a field sequence signal (fseq) which is high in the first of 4 respectively 8 fields. on the rcv2 port, the ic can provide a horizontal pulse with programmable start and stop phase; this pulse can be inhibited in the vertical blanking period to build up e.g. a composite blanking signal. the phase of the pulses output on rcv1 or rcv2 are referenced to the vp port, polarity of both signals is selectable. the denc2-m is always the timing master for the source at the mp input. the ic provides two signals for synchronizing this source: on the rcm1 port the same signals as on rcv1 (as output) are available; on rcm2 the ic provides a horizontal pulse with programmable start and stop phase. the length of a field also start and end of its active part can be programmed. the active part of a field always starts at the beginning of a line. control interface denc2-m contains two control interfaces: an i 2 c-bus slave transceiver and 8-bit parallel microprocessor interface. the interfaces cannot be used simultaneously. the i 2 c-bus interface is a standard slave transceiver, supporting 7-bit slave addresses and 100 kbits/s guaranteed transfer rate. it uses 8-bit subaddressing with an auto-increment function. all registers are write only, except one readable status byte. two i 2 c-bus slave addresses can be selected (pin sel_mpu must be low): 88h: low at pin 61 8ch: high at pin 61. the parallel interface is defined by: d7 to d0 data bus cs active-low chip select signal r w read/not write signal, low for a write cycle dtack 680xx style data acknowledge (handshake), active-low a0 register select, low selects address, high selects data. the parallel interface uses two registers, one auto-incremental containing the current address of a control register (equals subaddress with i 2 c-bus control), one containing actual data. the currently addressed register is mapped to the corresponding control register. the status byte can be read optionally via a read access to the address register, no other read access is provided. input levels and formats denc2-m expects digital yuv data with levels (digital codes) in accordance with ccir 601. deviating amplitudes of the colour difference signals can be compensated by independent gain control setting, while gain for luminance is set to predefined values, distinguishable for 7.5 ire set-up or without set-up. the mpeg port accepts only 8-bit multiplexed ccir 656 compatible data. if the i 2 c-bus interface is used, the vp port can handle both formats, 8-bit multiplexed cb-y-cr data on the vp lines, or the 16-bit dtv2 format with the y signal on the vp lines and the uv signal on the dp port. reference levels are measured with a colour bar, 100% white, 100% amplitude and 100% saturation.
1996 jul 08 10 philips semiconductors preliminary speci?cation digital video encoder (denc2-m) saa7188a table 1 ccir signal component levels table 2 8-bit multiplexed format (similar to ccir 656) table 3 16-bit multiplexed format (dtv2 format) signal ire digital level code y 016 straight binary 50 126 100 235 cb bottom peak 16 straight binary colourless 128 top peak 240 cr bottom peak 16 straight binary colourless 128 top peak 240 time format 01234567 sample cb 0 y 0 cr 0 y 1 cb 2 y 2 cr 2 y 3 luminance pixel number 0 1 2 3 colour pixel number 0 2 time format 01234567 sample y line y 0 y 1 y 2 y 3 sample uv line cb 0 cr 0 cb 2 cr 2 luminance pixel number 0 1 2 3 colour pixel number 0 2
1996 jul 08 11 philips semiconductors preliminary speci?cation digital video encoder (denc2-m) saa7188a bit allocation map table 4 slave receiver (slave address 88h or 8ch) register function sub address data byte (note 1) d7 d6 d5 d4 d3 d2 d1 d0 null 00 00000000 01 to 38 null 39 00000000 input port control 3a cbenb 0 0 v656 vy2c vuv2c my2c muv2c osd lut y0 42 osdy07 osdy06 osdy05 osdy04 osdy03 osdy02 osdy01 osdy00 osd lut u0 43 osdu07 osdu06 osdu05 osdu04 osdu03 osdu02 osdu01 osdu00 osd lut v0 44 osdv07 osdv06 osdv05 osdv04 osdv03 osdv02 osdv01 osdv00 45 to 56 osd lut y7 57 osdy77 osdy76 osdy75 osdy74 osdy73 osdy72 osdy71 osdy70 osd lut u7 58 osdu77 osdu76 osdu75 osdu74 osdu73 osdu72 osdu71 osdu70 osd lut v7 59 osdv77 osdv76 osdv75 osdv74 osdv73 osdv72 osdv71 osdv70 chrominance phase 5a chps7 chps6 chps5 chps4 chps3 chps2 chps1 chps0 gain u 5b gainu7 gainu6 gainu5 gainu4 gainu3 gainu2 gainu1 gainu0 gain v 5c gainv7 gainv6 gainv5 gainv4 gainv3 gainv2 gainv1 gainv0 gain u msb, black level 5d gainu8 0 blckl5 blckl4 blckl3 blckl2 blckl1 blckl0 gain v msb, blanking level 5e gainv8 0 blnnl5 blnnl4 blnnl3 blnnl2 blnnl1 blnnl0 null 5f 00000000 cross-colour select 60 ccrs1 ccrs0 000000 standard control 61 0 down inpi1 ygs rtce scbw pal fise burst amplitude 62 sqp bsta6 bsta5 bsta4 bsta3 bsta2 bsta1 bsta0 subcarrier 0 63 fsc07 fsc06 fsc05 fsc04 fsc03 fsc02 fsc01 fsc00 subcarrier 1 64 fsc15 fsc14 fsc13 fsc12 fsc11 fsc10 fsc09 fsc08 subcarrier 2 65 fsc23 fsc22 fsc21 fsc20 fsc19 fsc18 fsc17 fsc16 subcarrier 3 66 fsc31 fsc30 fsc29 fsc28 fsc27 fsc26 fsc25 fsc24 line 21 odd 0 67 l21o07 l21o06 l21o05 l21o04 l21o03 l21o02 l21o01 l21o00 line 21 odd 1 68 l21o17 l21o16 l21o15 l21o14 l21o13 l21o12 l21o11 l21o10 line 21 even 0 69 l21e07 l21e06 l21e05 l21e04 l21e03 l21e02 l21e01 l21e00 line 21 even 1 6a l21e17 l21e16 l21e15 l21e14 l21e13 l21e12 l21e11 l21e10 encoder control, cc line 6b modin1 modin0 0 sccln4 sccln3 sccln2 sccln1 sccln0
1996 jul 08 12 philips semiconductors preliminary speci?cation digital video encoder (denc2-m) saa7188a note 1. all bits labelled 0 are reserved. they must be programmed with logic 0. rcv port control 6c srcv11 srcv10 trcv2 orcv1 prcv1 cblf orcv2 prcv2 rcm, cc mode 6d 0000 srcm11 srcm10 ccen1 ccen0 horizontal trigger 6e htrig7 htrig6 htrig5 htrig4 htrig3 htrig2 htrig1 htrig0 horizontal trigger 6f 00000 htrig10 htrig09 htrig08 f sc reset mode, vertical trigger 70 phres1 phres0 sblbn vtrig4 vtrig3 vtrig2 vtrig1 vtrig0 begin mp request 71 bmrq7 bmrq6 bmrq5 bmrq4 bmrq3 bmrq2 bmrq1 bmrq0 end mp request 72 emrq7 emrq6 emrq5 emrq4 emrq3 emrq2 emrq1 emrq0 msbs mp request 73 0 emrq10 emrq09 emrq08 0 bmrq10 bmrq09 bmrq08 null 74 00000000 null 75 00000000 null 76 00000000 begin rcv2 output 77 brcv7 brcv6 brcv5 brcv4 brcv3 brcv2 brcv1 brcv0 end rcv2 output 78 ercv7 ercv6 ercv5 ercv4 ercv3 ercv2 ercv1 ercv0 msbs rcv2 output 79 0 ercv10 ercv09 ercv08 0 brcv10 brcv09 brcv08 field length 7a flen7 flen6 flen5 flen4 flen3 flen2 flen1 flen0 first active line 7b fal7 fal6 fal5 fal4 fal3 fal2 fal1 fal0 last active line 7c lal7 lal6 lal5 lal4 lal3 lal2 lal1 lal0 msbs ?eld control 7d 0 0 lal8 fal8 0 0 flen9 flen8 register function sub address data byte (note 1) d7 d6 d5 d4 d3 d2 d1 d0
1996 jul 08 13 philips semiconductors preliminary speci?cation digital video encoder (denc2-m) saa7188a i 2 c-bus format table 5 i 2 c-bus address; see table 6 table 6 explanation of table 5 notes 1. x is the read/write control bit; x = logic 0 is order to write; x = logic 1 is order to read, no subaddressing with read. 2. if more than 1 byte data is transmitted, then auto-increment of the subaddress is performed. slave receiver table 7 subaddress 3a s slave address ack subaddress ack data 0 ack -------- data n ack p part description s start condition slave address 1000100x or 1000110x (note 1) ack acknowledge, generated by the slave subaddress (note 2) subaddress byte data data byte -------- continued data bytes and acks p stop condition data byte logic level description muv2c 0 cb/cr data at mp is twos complement. 1 cb/cr data at mp is straight binary. default after reset. my2c 0 y data at mp is twos complement. 1 y data at mp is straight binary. default after reset. vuv2c 0 cb/cr data input to vp or dp is twos complement. default after reset. 1 cb/cr data input to vp or dp is straight binary. vy2c 0 y data input to vp is twos complement. default after reset. 1 y data input to vp is straight binary. v656 0 selects yuv 422 format on vp (8 lines y) and dp (8 lines multiplexed cb/cr). 1 selects ccir 656 compatible format on vp (8 lines cb, y, cr). default after reset. cbenb 0 data from input ports is encoded. default after reset. 1 colour bar with programmable colours (entries of osd_luts) is encoded. the luts are read in upward order from index 0 to index 7.
1996 jul 08 14 philips semiconductors preliminary speci?cation digital video encoder (denc2-m) saa7188a table 8 subaddress 42 to 59 notes 1. contents of osd look-up tables. all 8 entries are 8-bits. data representation is in accordance with ccir 601 (y, cb, cr), but twos complement, e.g. for a 100 100 (upper number) or 100 75 (lower number) colour bar. 2. for normal colour bar with cbenb = logic 1. table 9 subaddress 5a table 10 subaddress 5b and 5d notes 1. gainu = - 2.17 nominal to +2.16 nominal. 2. gainu = - 2.05 nominal to +2.04 nominal. colour data byte (note 1) index (note 2) osdy osdu osdv white 107 (6bh) 0 (00h) 0 (00h) 0 107 (6bh) 0 (00h) 0 (00h) yellow 82 (52h) 144 (90h) 18 (12h) 1 34 (22h) 172 (ach) 14 (0eh) cyan 42 (2ah) 38 (26h) 144 (90h) 2 03 (03h) 29 (1dh) 172 (ach) green 17 (11h) 182 (b6h) 162 (a2h) 3 240 (f0h) 200 (c8h) 185 (b9h) magenta 234 (eah) 74 (4ah) 94 (5eh) 4 212 (d4h) 56 (38h) 71 (47h) red 209 (d1h) 218 (dah) 112 (70h) 5 193 (c1h) 227 (e3h) 84 (54h) blue 169 (a9h) 112 (70h) 238 (eeh) 6 163 (a3h) 84 (54h) 242 (f2h) black 144 (90h) 0 (00h) 0 (00h) 7 144 (90h) 0 (00h) 0 (00h) data byte description chps phase of encoded colour subcarrier (including burst) relative to horizontal sync. can be adjusted in steps of 360 or 256 degrees. data byte description conditions remarks gainu variable gain for cb signal; input representation accordance with ccir 601 white-to-black = 92.5 ire (1) gainu = 0 output subcarrier of u contribution = 0 gainu = 118 (76h) output subcarrier of u contribution = nominal white-to-black = 100 ire (2) gainu = 0 output subcarrier of u contribution = 0 gainu = 125 (7dh) output subcarrier of u contribution = nominal
1996 jul 08 15 philips semiconductors preliminary speci?cation digital video encoder (denc2-m) saa7188a table 11 subaddress 5c and 5e notes 1. gainv = - 1.55 nominal to +1.55 nominal. 2. gainv = - 1.46 nominal to +1.46 nominal. table 12 subaddress 5d notes 1. output black level/ire = blckl 25/63 + 24; recommended value: blckl = 60 (3ch) normal. 2. output black level/ire = blckl 26/63 + 24; recommended value: blckl = 45 (2dh) normal. table 13 subaddress 5e notes 1. output black level/ire = blnnl 25/63 + 17; recommended value: blnnl = 58 (3ah) normal. 2. output black level/ire = blnnl 26/63 + 17; recommended value: blnnl = 63 (3fh) normal. data byte description conditions remarks gainv variable gain for cr signal; input representation accordance with ccir 601 white-to-black = 92.5 ire (1) gainv = 0 output subcarrier of v contribution = 0 gainv = 165 (a5h) output subcarrier of v contribution = nominal white-to-black = 100 ire (2) gainv = 0 output subcarrier of v contribution = 0 gainv = 175 (afh) output subcarrier of v contribution = nominal data byte description conditions remarks blckl variable black level; input representation accordance with ccir 601 white-to-sync = 140 ire (1) blckl = 0 output black level = 24 ire blckl = 63 (3fh) output black level = 49 ire white-to-sync = 143 ire (2) blckl = 0 output black level = 24 ire blckl = 63 (3fh) output black level = 50 ire data byte description conditions remarks blnnl variable blanking level white-to-sync = 140 ire (1) blnnl = 0 output blanking level = 17 ire blnnl = 63 (3fh) output blanking level = 42 ire white-to-sync = 143 ire (2) blnnl = 0 output blanking level = 17 ire blnnl = 63 (3fh) output blanking level = 43 ire
1996 jul 08 16 philips semiconductors preliminary speci?cation digital video encoder (denc2-m) saa7188a table 14 subaddress 60 (ccrs; select cross colour reduction ?lter in luminance) table 15 subaddress 61 data byte function ccrs1 ccrs0 0 0 no cross colour reduction (for overall transfer characteristic of luminance see fig.5) 0 1 cross colour reduction #1 active (for overall transfer characteristic see fig.5) 1 0 cross colour reduction #2 active (for overall transfer characteristic see fig.5) 1 1 cross colour reduction #3 active (for overall transfer characteristic see fig.5) data byte logic level description fise 0 864 total pixel clocks per line 1 858 total pixel clocks per line; default after reset pal 0 ntsc encoding (non-alternating v component); default after reset 1 pal encoding (alternating v component) scbw 0 enlarged bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see figs 3 and 4) 1 standard bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see figs 3 and 4); default after reset rtce 0 no real time control of generated subcarrier frequency; default after reset 1 real time control of generated subcarrier frequency through saa7151b (timing see fig.9) ygs 0 luminance gain for white-to-black 100 ire 1 luminance gain for white-to-black 92.5 ire including 7.5 ire set-up of black; default after reset inpi 0 pal switch phase is nominal; default after reset 1 pal switch phase is inverted compared to nominal down 0 dacs in normal operational mode; default after reset 1 dacs forced to lowest output voltage
1996 jul 08 17 philips semiconductors preliminary speci?cation digital video encoder (denc2-m) saa7188a table 16 subaddress 62 notes 1. recommended value: bsta = 102 (66h). 2. recommended value: bsta = 72 (48h). 3. recommended value: bsta = 106 (6ah). 4. recommended value: bsta = 75 (4bh). table 17 subaddress 63 to 66 (four bytes to program subcarrier frequency) note 1. examples: a) ntsc-m: f sc = 227.5, f llc = 1716 ? fsc = 569408543 (21f07c1fh). b) pal-b/g: f sc = 283.7516, f llc = 1728 ? fsc = 705268427 (2a098acbh). data byte description conditions remarks bsta amplitude of colour burst; input representation accordance with ccir 601 white-to-black = 92.5 ire; burst = 40 ire; ntsc encoding bsta = 0 to 1.25 nominal (1) white-to-black = 92.5 ire; burst = 40 ire; pal encoding bsta = 0 to 1.76 nominal (2) white-to-black = 100 ire; burst = 43 ire; ntsc encoding bsta = 0 to 1.20 nominal (3) white-to-black = 100 ire; burst = 43 ire; pal encoding bsta = 0 to 1.67 nominal (4) sqp subcarrier real time logic 0 control from saa7151b digital colour decoder logic 1 not supported in current version, do not use data byte description conditions remarks fsc0 to fsc3 f sc = subcarrier frequency (in multiples of line frequency); f llc = clock frequency (in multiples of line frequency) see note 1 fsc3 = most signi?cant byte fsc0 = least signi?cant byte fsc round f sc f llc ---------- 2 32 ? ? ?? =
1996 jul 08 18 philips semiconductors preliminary speci?cation digital video encoder (denc2-m) saa7188a table 18 subaddress 67 to 6a note 1. lsbs of the respective bytes are encoded immediately after run-in and framing code, the msbs of the respective bytes have to carry the parity bit, in accordance with the de?nition of line 21 encoding format. table 19 subaddress 6b note 1. line = (sccln + 4) for m systems; line = (sccln + 1) for other systems. table 20 logic levels and function of modin data byte (1) description l21od2 ?rst byte of captioning data, odd ?eld l21od3 second byte of captioning data, odd ?eld l21ed0 ?rst byte of extended data, even ?eld l21ed1 second byte of extended data, even ?eld data byte description sccln selects the actual line, where closed caption or extended data are encoded; see note 1 modin de?nes video data of mp port or vp (dp) port to be encoded; see table 20 data byte function modin1 modin0 0 0 unconditionally from mp port 0 1 from mp port, if pin sel_ed = high; otherwise from vp port 1 0 unconditionally from vp port 1 1 from vp port, if pin sel_ed = high; otherwise from mp port
1996 jul 08 19 philips semiconductors preliminary speci?cation digital video encoder (denc2-m) saa7188a table 21 subaddress 6c table 22 logic levels and function of srcv1 table 23 subaddress 6d data byte logic level description prcv2 0 polarity of rcv2 as output is active high, rising edge is taken when input, respectively; default after reset 1 polarity of rcv2 as output is active low, falling edge is taken when input, respectively orcv2 0 pin rcv2 is switched to input; default after reset 1 pin rcv2 is switched to output cblf 0 if orcv2 = high, pin rcv2 provides an href signal (horizontal reference pulse that is high during active portion of line, also during vertical blanking interval); default after reset if orcv2 = low, signal input to rcv2 is used for horizontal synchronization only (if trcv2 = 1); default after reset 1 if orcv2 = high, pin rcv2 provides a cbn signal (reference pulse that is high during active video, excluding vertical blanking interval) if orcv2 = low, signal input to rcv2 is used for horizontal synchronization (if trcv2 = 1) also as an internal blanking signal prcv1 0 polarity of rcv1 as output is active high, rising edge is taken when input, respectively; default after reset 1 polarity of rcv1 as output is active low, falling edge is taken when input, respectively orcv1 0 pin rcv1 is switched to input; default after reset 1 pin rcv1 is switched to output trcv2 0 horizontal synchronization is taken from rcv1 port; default after reset 1 horizontal synchronization is taken from rcv2 port srcv1 - de?nes signal type on pin rcv1; see table 22 data byte as output as input function srcv11 srcv10 0 0 vs vs vertical sync each ?eld; default after reset 0 1 fs fs frame sync (odd/even) 1 0 fseq fseq field sequence, vertical sync every fourth ?eld (fise = 1) or eighth ?eld (fise = 0) 11 -- not applicable data byte description ccen enables individual line 21 encoding; see table 24 srcm de?nes signal type on pin rcm1; see table 25
1996 jul 08 20 philips semiconductors preliminary speci?cation digital video encoder (denc2-m) saa7188a table 24 logic levels and function of ccen table 25 logic levels and function of srcm table 26 subaddress 6e to 6f table 27 subaddress 70 note 1. if cross-colour reduction is programmed, it is active between fal and lal in both events. data byte function ccen1 ccen0 0 0 line 21 encoding off 0 1 enables encoding in ?eld 1 (odd) 1 0 enables encoding in ?eld 2 (even) 1 1 enables encoding in both ?elds data byte as output function srcm1 srcm0 0 0 vs vertical sync each ?eld 0 1 fs frame sync (odd/even) 1 0 fseq field sequence, vertical sync every fourth ?eld (fise = 1) or eighth ?eld (fise = 0) 11 - not applicable data byte description htrig sets the horizontal trigger phase related to signal on rcv1 or rcv2 input values above 1715 (fise = 1) or 1727 (fise = 0) are not allowed increasing htrig decreases delays of all internally generated timing signals reference mark: analog output horizontal sync (leading slope) coincides with active edge of rcv used for triggering at htrig = 032h data byte logic level description vtrig - sets the vertical trigger phase related to signal on rcv1 input increasing vtrig decreases delays of all internally generated timing signals, measured in half lines variation range of vtri g=0to31 (1fh) sblbn 0 vertical blanking is de?ned by programming of fal and lal 1 vertical blanking is forced automatically at least during ?eld synchronization and equalization pulses; note 1 phres - selects the phase reset mode of the colour subcarrier generator; see table 28
1996 jul 08 21 philips semiconductors preliminary speci?cation digital video encoder (denc2-m) saa7188a table 28 logic levels and function of phres table 29 subaddress 71 to 73 table 30 subaddress 77 to 79 table 31 subaddress 7a to 7d s ubaddresses in subaddresses 5b, 5c, 5d, 5e and 62 all ire values are rounded up. data byte function phres1 phres0 0 0 no reset 0 1 reset every two lines 1 0 reset every eight ?elds 1 1 reset every four ?elds data byte description bmrq beginning of mp request signal (rcm2) values above 1715 (fise = 1) or 1727 (fise = 0) are not allowed ?rst active pixel at analog outputs (corresponding input pixel coinciding with rcm2) at bmrq = 0f9h (115h) emrq end of mp request signal (rcm2) values above 1715 (fise = 1) or 1727 (fise = 0) are not allowed last active pixel at analog outputs (corresponding input pixel coinciding with rcm2) at emrq = 686h (690h) data byte description brcv beginning of output signal on rcv2 pin values above 1715 (fise = 1) or 1727 (fise = 0) are not allowed ?rst active pixel at analog outputs (corresponding input pixel coinciding with rcv2) at brcv = 0f9h (115h) ercv end of output signal on rcv2 pin values above 1715 (fise = 1) or 1727 (fise = 0) are not allowed last active pixel at analog outputs (corresponding input pixel coinciding with rcv2) at ercv = 686h (690h) data byte description flen length of a ?eld = flen + 1, measured in half lines valid range is limited to 524 to 1022 (fise = 1) respectively 624 to 1022 (fise = 0), flen should be even fal ?rst active line after vertical blanking interval = fal + 1, measured in lines fal = 0 coincides with the ?rst ?eld synchronization pulse lal last active line before vertical blanking interval = lal + 1, measured in lines lal = 0 coincides with the ?rst ?eld synchronization pulse
1996 jul 08 22 philips semiconductors preliminary speci?cation digital video encoder (denc2-m) saa7188a slave transmitter table 32 slave transmitter (slave address 89h or 8dh) table 33 no subaddress register function subaddress data byte d7 d6 d5 d4 d3 d2 d1 d0 status byte - ver2 ver1 ver0 ccrdo ccrde fsq2 fsq1 fsq0 data byte description ver version identi?cation of the device. it will be changed with all versions of the ic that have different programming models. current version is 011 binary. ccrde closed caption bytes of the even ?eld have been encoded. the bit is reset after information has been written to the subaddresses 69 and 6a. it is set immediately after the data have been encoded. ccrdo closed caption bytes of the odd ?eld have been encoded. the bit is reset after information has been written to the subaddresses 67 and 68. it is set immediately after the data have been encoded. fsq state of the internal ?eld sequence counter. bit 0 (fsq0) gives the odd/even information; odd = low, even = high.
1996 jul 08 23 philips semiconductors preliminary speci?cation digital video encoder (denc2-m) saa7188a fig.3 chrominance transfer characteristic 1. handbook, full pagewidth 6 8 10 12 14 6 0 024 mbe737 - 6 - 12 - 18 - 30 - 24 - 36 - 42 - 54 - 48 f (mhz) g v (db) (1) (2) (1) scbw = 1. (2) scbw = 0. fig.4 chrominance transfer characteristic 2. handbook, halfpage 0 0.4 0.8 1.6 2 0 - 4 - 6 - 2 mbe735 1.2 f (mhz) g v (db) (1) (2) (1) scbw = 1. (2) scbw = 0.
1996 jul 08 24 philips semiconductors preliminary speci?cation digital video encoder (denc2-m) saa7188a fig.5 luminance transfer characteristic 1. handbook, full pagewidth 6 8 10 12 14 6 0 024 mbe738 - 6 - 12 - 18 - 30 - 24 - 36 - 42 - 54 - 48 f (mhz) g v (db) (1) (2) (3) (4) (1) ccrs1 = 0; ccrs0 = 1. (2) ccrs1 = 1; ccrs0 = 0. (3) ccrs1 = 1; ccrs0 = 1. (4) ccrs1 = 0; ccrs0 = 0. fig.6 luminance transfer characteristic 2. handbook, halfpage 02 6 1 0 - 1 - 2 - 3 - 4 - 5 mbe736 4 f (mhz) g v (db) ccrs1 = 0; ccrs0 = 0.
1996 jul 08 25 philips semiconductors preliminary speci?cation digital video encoder (denc2-m) saa7188a characteristics v ddd = 4.5 to 5.5 v; t amb = 0 to 70 c; unless otherwise speci?ed. symbol parameter conditions min. max. unit supply v ddd digital supply voltage 4.5 5.5 v v dda analog supply voltage 4.75 5.25 v i ddd digital supply current note 1 - 170 ma i dda analog supply current note 1 - 55 ma inputs v il low level input voltage (except llc, sda, scl, ap, sp and xtali) - 0.5 +0.8 v v ih high level input voltage (except llc, sda, scl, ap, sp and xtali) 2.0 v ddd + 0.5 v high level input voltage (llc) 2.4 v ddd + 0.5 v i li input leakage current - 1 m a c i input capacitance clocks operating - 10 pf data available - 8pf i/os at high impedance - 8pf outputs v ol low level output voltage (except sda and xtalo) note 2 0 0.6 v v oh high level output voltage (except llc, sda, dt ack and xtalo) note 2 2.4 v ddd + 0.5 v high level output voltage (llc) note 2 2.6 v ddd + 0.5 v i 2 c-bus; sda and scl v il low level input voltage - 0.5 +1.5 v v ih high level input voltage 3.0 v ddd + 0.5 v i i input current v i = low or high - 10 m a v ol low level output voltage (sda) i ol =3ma - 0.4 v i o output current during acknowledge 3 - ma clock timing (llc) t llc cycle time note 3 34 41 ns d duty factor t high /t llc note 4 40 60 % t r rise time note 3 - 5ns t f fall time note 3 - 6ns
1996 jul 08 26 philips semiconductors preliminary speci?cation digital video encoder (denc2-m) saa7188a input timing t su;cref input data set-up time (cref) 6 - ns t hd;cref input data hold time (cref) 3 - ns t su input data set-up time (any other except sel_mpu, cdir, r w/scl, a0/sda, cs/sa, reset, ap and sp) 6 - ns t hd input data hold time (any other except sel_mpu, cdir, r w/scl, a0/sda, cs/sa, reset, ap and sp) 3 - ns crystal oscillator f n nominal frequency (usually 27 mhz) 3rd harmonic - 30 mhz d f/f n permissible deviation of nominal frequency note 5 - 50 +50 10 - 6 c rystal specification t amb operating ambient temperature 0 70 c c l load capacitance 8 - pf r s series resonance resistance - 80 w c 1 motional capacitance (typical) 1.5 - 20% 1.5 +20% ff c 0 parallel capacitance (typical) 3.5 - 20% 3.5 +20% pf mpu interface timing t as address set-up time note 6 9 - ns t ah address hold time 0 - ns t r ws read/write set-up time note 6 9 - ns t r wh read/write hold time 0 - ns t dd data valid from cs (read) notes 7, 8 and 9; n = 9 - 400 ns t df data bus ?oating from cs (read) notes 7 and 8; n = 5 - 255 ns t ds data bus set-up time (write) note 6 9 - ns t dh data bus hold time (write) note 6 9 - ns t acs acknowledge delay from cs notes 7 and 8; n = 11 - 475 ns t csd cs high from acknowledge 0 - ns t dat dt ack ?oating from cs high notes 7 and 8; n = 7 - 330 ns data and reference signal output timing c l output load capacitance 7.5 40 pf t oh output hold time 4 - ns t od output delay time cref in output mode - 25 ns symbol parameter conditions min. max. unit
1996 jul 08 27 philips semiconductors preliminary speci?cation digital video encoder (denc2-m) saa7188a notes 1. at maximum supply voltage with highly active input signals. 2. the levels have to be measured with load circuits of 1.2 k w to 3.0 v (standard ttl load) and c l = 25 pf. 3. the data is for both input and output direction. 4. with llc in input mode. in output mode, with a crystal connected to xtalo/xtali duty factor is typically 50%. 5. if an internal oscillator is used, crystal deviation of nominal frequency (f n ) is directly proportional to the deviation of subcarrier frequency and line/field frequency. 6. the value is calculated via equation 7. the value depends on the clock frequency. the numbers given are calculated with f llc = 27 mhz. 8. the values given are calculated via equation 9. the falling edge of dtack will always occur 1 llc after data is valid. 10. for full digital range, without load, v dda = 5.0 v. the typical voltage swing is 2.0 v, the typical minimum output voltage (digital zero at dac) is 0.2 v. chroma, y and cvbs outputs v o(p-p) output signal voltage (peak-to-peak value) note 10 1.9 2.1 v r i internal serial resistance 18 35 w r l output load resistance 80 -w b output signal bandwidth of dacs - 3db 10 - mhz ile lf integral linearity error of dacs - 2 lsb dle lf differential linearity error of dacs - 1 lsb symbol parameter conditions min. max. unit tt su t hd + = t dmax t od nt llc t llc t su ++ + =
1996 jul 08 28 philips semiconductors preliminary speci?cation digital video encoder (denc2-m) saa7188a fig.7 clock data timing. handbook, full pagewidth mbe742 llc clock output 0.6 v 1.5 v 2.6 v 2.0 v 0.8 v 2.4 v 0.6 v input data output data not valid valid valid not valid valid valid llc clock input 0.8 v 1.5 v 2.4 v t high t hd; dat t llc t high t llc t d t hd; dat t hd; dat t su; dat t f t f t r t r fig.8 digital tv timing. the data demultiplexing phase is coupled to the internal horizontal phase. the cref signal applies only for the 16 lines digital tv format, because these signals are only valid in 13.5 mhz. the phase of the rcv2 signal is programmed to 0f9h (115h for 50 hz) in this example in output mode (brcv2). handbook, full pagewidth llc cref vp(n) y(0) cb(0) y(1) cr(0) y(2) cb(2) y(3) cr(2) y(4) cb(4) dp(n) rcv2 mbe739
1996 jul 08 29 philips semiconductors preliminary speci?cation digital video encoder (denc2-m) saa7188a fig.9 rtci timing. (1) sequence bit: pal = logic 0 then (r - y) line normal; pal = logic 1 then (r - y) line inverted. ntsc = logic 0 then no change. (2) reserved bits: 236 with 50 hz systems; 233 with 60 hz systems. handbook, full pagewidth 128 13 0 21 rtci hpll increment h/l transition count start 4 bits reserved valid sample invalid sample not used in denc2-m 0 sequence bit (1) 5 bits reserved 8/llc reserved (2) mbg270 fscpll increment
1996 jul 08 30 philips semiconductors preliminary speci?cation digital video encoder (denc2-m) saa7188a fig.10 mpu interface timing (read cycle). handbook, full pagewidth a0 cs rw d(7 to 0) dtack t as t ah t rws t rwh t dat t acs t df t csd t dd mbg268 fig.11 mpu interface timing (write cycle). handbook, full pagewidth a0 cs rw d(7 to 0) dtack t as t ah t rws t rwh t dat t acs t df t csd t ds mbg269
1996 jul 08 31 philips semiconductors preliminary speci?cation digital video encoder (denc2-m) saa7188a application information handbook, full pagewidth (1) (3) 49 (1) 51 (1) 53 52 v ssa 0.62 v (p-p) (2) chroma 75 w 75 35 w 20 w 20 w 12 w 35 w 35 w w 75 w 1.0 v (p-p) (2) y 1.23 v (p-p) (2) cvbs v ssa v ssa v ssa 48 50 v dda2 v dda1 v dda3 dac3 dac2 dac1 i i v refh 54 55 47 46 v refl 1, 8, 19, 28, 35, 42, 62 v ssd1 to v ssd7 0.1 m f 0.1 m f 15 k w v ssa v ssa v dda4 56 + 5 v analog 0.1 m f v ssa 0.1 m f v ssa 0.1 m f v ssa 67 37 v ddd2 v ddd3 v ddd1 17 0.1 m f v ssd 0.1 m f v ssd 0.1 m f v ssd + 5 v digital 10 pf 3rd harmonic x1 27.0 mhz xtal0 40 xtal1 41 10 pf 1 nf v ssd 10 m h digital inputs and outputs saa7188a mbg267 fig.12 application environment of the denc2-m. (1) typical value. (2) for 100 100 colour bar. (3) philips 12nc ordering code: 4312 065 02341.
1996 jul 08 32 philips semiconductors preliminary speci?cation digital video encoder (denc2-m) saa7188a package outline references outline version european projection issue date iec jedec eiaj note 1. plastic or metal protrusions of 0.01 inches maximum per side are not included. sot188-2 44 60 68 1 9 10 26 43 27 61 detail x (a ) 3 b p w m a 1 a a 4 l p b 1 b k 1 k x y e e b d h e h v m b d z d a z e e v m a pin 1 index 112e10 mo-047ac 0 5 10 mm scale 92-11-17 95-03-11 plcc68: plastic leaded chip carrier; 68 leads sot188-2 unit a a min. max. max. max. max. 1 a 4 b p e (1) (1) (1) eh e z y w v b mm 4.57 4.19 0.51 3.30 0.53 0.33 0.021 0.013 1.27 0.51 2.16 45 o 0.18 0.10 0.18 dimensions (millimetre dimensions are derived from the original inch dimensions) d (1) 24.33 24.13 h d 25.27 25.02 e z 2.16 d b 1 0.81 0.66 k 1.22 1.07 k 1 0.180 0.165 0.020 0.13 a 3 0.25 0.01 0.05 0.020 0.085 0.007 0.004 0.007 l p 1.44 1.02 0.057 0.040 0.958 0.950 24.33 24.13 0.958 0.950 0.995 0.985 25.27 25.02 0.995 0.985 e e e d 23.62 22.61 0.930 0.890 23.62 22.61 0.930 0.890 0.085 0.032 0.026 0.048 0.042 e e inches d e
1996 jul 08 33 philips semiconductors preliminary speci?cation digital video encoder (denc2-m) saa7188a soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all plcc packages. the choice of heating method may be influenced by larger plcc packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. for more information, refer to the drypack chapter in our quality reference handbook (order code 9398 510 63011). reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. wave soldering wave soldering techniques can be used for all plcc packages if the following conditions are observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow. the package footprint must incorporate solder thieves at the downstream corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1996 jul 08 34 philips semiconductors preliminary speci?cation digital video encoder (denc2-m) saa7188a definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1996 jul 08 35 philips semiconductors preliminary speci?cation digital video encoder (denc2-m) saa7188a notes
internet: http://www.semiconductors.philips.com/ps/ (1) saa7188a_2 june 26, 1996 11:51 am philips semiconductors C a worldwide company ? philips electronics n.v. 1996 sca50 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 83749, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 926 5361, fax. +7 095 564 8323 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220, 5th floor, suite 51, 04552-903 s?o paulo, s?o paulo - sp, brazil, tel. +55 11 821 2333, fax. +55 11 829 1849 spain: balmes 22, 08007 barcelona, tel. +34 3 301 6312, fax. +34 3 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 632 2000, fax. +46 8 632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2686, fax. +41 1 481 7730 taiwan: philips taiwan ltd., 23-30f, 66, chung hsiao west road, sec. 1, p.o. box 22978, taipei 100, tel. +886 2 382 4443, fax. +886 2 382 4444 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine: philips ukraine, 2a akademika koroleva str., office 165, 252148 kiev, tel. +380 44 476 0297/1642, fax. +380 44 476 6991 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381, fax. +1 708 296 8556 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 825 344, fax.+381 11 635 777 for all other countries apply to: philips semiconductors, marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381, fax. +1 708 296 8556 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 1949 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 615 800, fax. +358 615 80920 france: 4 rue du port-aux-vins, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 52 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros, tel. +30 1 4894 339/911, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, shivsagar estate, a block, dr. annie besant rd. worli, mumbai 400 018, tel. +91 22 4938 541, fax. +91 22 4938 722 indonesia: see singapore ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 648 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +1 800 234 7381, fax. +1 708 296 8556 middle east: see italy printed in the netherlands 657021/1200/02/pp36 date of release: 1996 jul 08 document order number: 9397 750 00944

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